1. Field of the Invention
The present invention relates generally to the field of integrated circuit testing and more particularly to an alignment mark in an integrated circuit die for aligning and navigating through an integrated circuit die.
2. Description of the Related Art
Once a newly designed integrated circuit has been formed on a silicon substrate, the integrated circuit must be thoroughly tested to ensure that the circuit performs as intended. Any portion of the integrated circuit which does not function properly must be identified so that it can be fixed by modifying the design of the integrated circuit. This process of testing an integrated circuit to identify problems with its design is known as debugging. After debugging the integrated circuit and correcting any problems with its design, the final fully functional integrated circuit designs are used to mass produce the integrated circuits in a manufacturing environment for consumer use.
During the debugging process, it is often necessary to navigate to certain locations in the integrated circuit to access certain integrated circuit nodes to, for example, collect important electrical data and information.
When debugging integrated circuits, it is sometimes impossible to obtain an electrical signal of interest from a pin or a bond pad from the integrated circuit package or die. In these instances, the electrical signal of interest is located at an internal integrated circuit node to which there is no connected probe point. In this situation, the substrate of the integrated circuit die is milled to expose the electrical node of interest to allow signals to be obtained directly. Naturally, it is important that the integrated circuit die is properly aligned so that probe point locations can be accurately located and determined. That is, the location of a probe hole must be determined with very high precision since the milling of an improperly placed hole can destroy the integrated circuit die if milled through an important integrated circuit components such as for example a transistor.
In order to ensure that an integrated circuit die is properly aligned and positioned so that navigation to the probe locations that will be milled can be precisely determined, alignment marks or fiducials are disposed directly in the integrated circuit die. FIG. 1 illustrates a surface view of the bottom of a controlled collapse chip connection (C4) chip 101 from which it is desired to collect electrical data from an integrated circuit node 103. C4 packaged chip 101 includes an integrated circuit die 111 mounted on a C4 package 113. Integrated circuit node 103 is buried beneath the surface of the integrated circuit die 111.
In order to probe integrated circuit node 103, the substrate above integrated circuit node 103 must be carefully removed so that integrated circuit node 103 can be exposed. Before the substrate of the integrated circuit die is milled, the precise location of integrated circuit node 103 must be accurately determined. In order to accurately determine the location of integrated circuit node 103, fiducials 105, 107 and 109 are formed in integrated circuit die 111 to provide points of reference when positioning and navigating through integrated circuit die 111. Since fiducials 105, 107 and 109 are formed beneath the substrate of integrated circuit die 111, they must also be exposed so that they can be accessed during the debug process.
FIG. 2 is an illustration of a cross-section of a fiducial 201. Fiducial 201 is disposed in a fiducial region located between dotted lines labeled 203 and 205 of an integrated circuit die. As shown in FIG. 2, fiducial 201 includes diffusion regions 207, 209 and 211 disposed in the substrate 213 of the integrated circuit die. Tungsten metal contacts 215, 217 and 219 are disposed in an oxide layer 221. Metal contacts 215, 217 and 219 provide electrical access to diffusion regions 207, 209 and 211 respectively. A metal pattern 223 is disposed beneath oxide layer 221. Metal pattern 223 provides alignment information for use during the positioning of and navigation through the integrated circuit die. An epoxy layer 225 is disposed beneath the integrated circuit die to bond the integrated circuit die to the C4 package (not shown).
In order to access fiducial 201 for alignment purposes, it is necessary to remove the substrate 213 within the fiducial region bounded by dotted lines 203 and 205. Present day techniques utilize a laser chemical etcher to remove most of substrate 213. The laser chemical etch procedure is stopped just short of reaching oxide layer 221. A focused ion beam (FIB) milling tool is used to remove the final remainder of substrate 213 down to oxide layer 221.
It is noted that the FIB milling tool must be used to mill the remaining portion of substrate 213 since metal contacts 215, 217 and 219 are exceptionally sensitive to laser chemical etching. In particular, it is noted that if a laser chemical etch is performed all the way down to oxide layer 221 using present day techniques, a catastrophic acceleration of the etching process occurs at metal contacts 215, 217 and 219. This catastrophic acceleration is the result of metal contacts 215, 217 and 219 being etched at a much higher rate than oxide layer 221 when using a laser chemical etch. Consequently, fiducial 201 may be damaged when contacts 215, 217 and 219 are etched with a laser chemical etcher. By stopping short of oxide layer 221 with the laser chemical etcher and completing the fiducial exposure process with an FIB milling tool, the risks of the catastrophic etching of contacts 215, 217 and 219 are reduced. The requirement of stopping short of oxide layer 221 and the additional of the step of milling the remaining portion of substrate 213 with a FIB milling tool results in an undesirable increase in the amount of time required to expose fiducial 201.
It is also noted that after substrate 213 is removed from fiducial 201, special care must be given to fiducial 201 to prevent excessive amounts of light from being exposed to the epoxy layer 225. For example, in some instances when epoxy layer 225 is exposed to an excessive amount of laser light, epoxy layer 225 may boil and expand, consequently rupturing the adjacent substrate and destroying the fiducial and the surrounding integrated circuit.
Therefore, what is desired is a fiducial that does not require both a laser chemical etch and a focused ion beam mill to expose a fiducial for aligning an integrated circuit. Such a fiducial should have the ability to be exposed using only a laser chemical etch. The fiducial should not suffer from the risk of being destroyed because of the catastrophic etching of metal contacts in the oxide layer. In addition, the fiducial should also have a minimal risk of being damaged from the exposure light to an epoxy underfill layer.